Sigma-delta A/D converter

ABSTRACT

Sigma-delta A/D converter having at least one analog signal input ( 1, 2 ) for applying an analog input signal, a subtraction element ( 3 ) having a plurality of capacitors ( 20 ) for sampling the input signal during a sampling phase, it being possible during an integration phase to switch the capacitors ( 20 ) to reference voltage sources ( 7, 8, 9 ) depending on control signals, an integrator ( 10 ) for integrating the output signal of the subtraction element ( 3 ) during the integration phase, a quantizer ( 13 ) for analog-to-digital conversion of the output signal of the integrator ( 10 ) for outputting a digitized output signal to a digital signal output ( 14 ), and having a control logic element ( 16 ) for generating the control signals in such a way that the current load of the reference voltage sources ( 7, 8, 9 ) is minimized during the integration phase.

[0001] The invention relates to a sigma-delta A/D converter with minimalcurrent load of the reference voltage sources.

[0002]FIG. 1 shows a block circuit diagram of a sigma-delta A/Dconverter according to the prior art. The sigma-delta A/D converterreceives an analog input signal at the input E, which is fed to asubtraction element S. In the subtraction element S the output signal ofa multi-bit D/A converter is subtracted from the analog input signal andis fed to an integrator. The integrator integrates the input signal andoutputs the integrated signal to a quantizer. The quantizer is ananalog-to-digital converter with a low resolution which outputs thedigitized output signal to an output A of the sigma-delta A/D converter.The digitized output signal is connected via a feedback line to theinput of the multi-bit D/A converter. The digitized output signal of thequantizer is converted by the multi-bit D/A converter into an analogsignal and is subtracted in the subtraction element S from the inputsignal at the input E.

[0003]FIG. 2 shows an embodiment of a sigma-delta A/D converteremploying SC circuitry (SC switched capacities: switchable capacitors).The prior art sigma-delta A/D converter shown in FIG. 2 is a fullydifferential sigma-delta A/D converter having two signal inputs V_(INA)and V_(INB). Also provided are reference voltage sources V_(REFP) andV_(REFN) which can be connected by controllable switching devices tocapacitors C_(1A), C_(2A), . . . C_(LA) as well as capacitors C_(1B),C_(2B), . . . C_(LB). The capacitors may furthermore be connected byswitching devices to the analog signal inputs V_(INA), V_(INB)

[0004] On the output side, the capacitors C_(1A), C₂A, . . . C_(LA) aswell as C_(1B), C_(2B), . . . C_(LB) can be connected by switchingdevices n and a common ground line to ground V_(GND) or to anintegrator.

[0005] In the sigma-delta A/D converter shown in FIG. 2, the integratorcontains an operational amplifier with one inverting and onenon-inverting input as well as two output lines, with integrationcapacitors C_(INT) being connected between the signal inputs and signaloutputs of the operational amplifier in each case. Connected downstreamof the integrator is a quantizer for analog-to-digital conversion of thevoltage between the two output lines of the operational amplifier. Thedigitized signal present at the output of the quantizer is fed via afeedback line to a control logic element which supplies control signalsfor controlling the switching devices.

[0006] During a sampling phase PH11, the capacitors C_(1A), C_(2A),C_(LA) are connected by switches on the one hand to the first analoginput line V_(INA) and on the other hand to ground V_(GND). During thesampling phase PHL1, the capacitors C_(1B), C_(2B), . . . C_(LB) areconnected by switching devices on the one hand to the second analoginput signal V_(INB) and on the other hand to ground V_(GND). During thesampling phase, all switches indicated by “PHL1” in FIG. 2 are closed.

[0007] Upon completion of the sampling phase PHL1, the switchesindicated by PH11 in FIG. 2 are opened and the capacitors C_(1A),C_(2A), . . . C_(LA) are connected by the switches indicated by PHL2 tothe non-inverting input (+) of the operational amplifier and to thefirst integration capacitor CintA for charge transfer. At the same time,the capacitors C_(1B), C_(2B), . . . C_(LB) are switched by the switchesindicated by PHL2 to the inverting input (−) of the operationalamplifier and to the second integration capacitor CintB for chargetransfer. At the same time, in each case the left capacitor plates ofthe capacitors C_(1A), C_(2A), . . . C_(LA) and C_(1B), C_(2B), . . .C_(LB) are connected to the reference voltage source V_(REFP) or to thereference voltage source V_(REFN) respectively in accordance with thecontrol instructions generated by the control logic element.

[0008] Upon completion of the integration phase PHL2, an output voltageV_(OUTP)(i) is present at the output of the integrator, i.e. between thetwo output lines of the operational amplifier, which output voltagedepends on the preceding value V_(OUTP)(i−1), the analog input voltageV_(INA) (i−½), the number of capacitors C_(jA) whose left capacitorplate is connected to the positive reference voltage source V_(REFP)during the integration phase, and the number n (i) of capacitors C_(jA)whose left capacitor plate is connected to the negative referencevoltage source V_(REFN) during the integration phase.

[0009] The output voltage V_(OUTP)(i) is obtained here using thefollowing equation: $\begin{matrix}{{{V_{O\quad U\quad T\quad P}(i)} = { {{V_{O\quad U\quad T\quad P}( {i - 1} )} + {{V_{INA}( {i - {1/2}} )} \cdot \frac{L \cdot C_{j\quad A}}{C_{int}}} - {{p(i)} \cdot}} \middle| \quad V_{REFP} \middle| {{\cdot \frac{C_{jA}}{C_{int}}} + {{n(i)} \cdot}} \middle| V_{REFN} \middle| {\cdot \frac{C_{jA}}{C_{int}}}  = {{{V_{O\quad U\quad T\quad P}( {i - 1} )} + {{V_{INA}( {i - {1/2}} )} \cdot \frac{L \cdot C_{j\quad A}}{C_{int}}} - {{( {{p(i)} - {n(i)}} ) \cdot V_{REF} \cdot \frac{C_{jA}}{C_{int}}}\quad {with}\quad V_{REF}}} = {| V_{REFP} | = | V_{REFN} |}}}};} & (1)\end{matrix}$

[0010] The number of capacitors C_(jA) whose left capacitor plate isconnected to the positive reference voltage source V_(REFP) during theintegration phase is obtained here using the following equation:$\begin{matrix}{{{p(i)} = {{{round}\lbrack {{L/2} \cdot ( {1 + \frac{V_{DIG}(i)}{V_{REF}}} )} \rbrack}<={L\quad {for}\quad {V_{DIG}(i)}}>=0}};} & (2)\end{matrix}$

[0011] where V_(DIG) is the output signal of the quantizer.

[0012] The number of capacitances C_(jA) whose capacitor plate isconnected to the negative reference voltage source V_(REFN) during theintegration phase is obtained using the following equation:$\begin{matrix}{{{n(i)} = {{{round}\lbrack {{L/2} \cdot ( {1 - \frac{V_{DIG}(i)}{V_{REF}}} )} \rbrack}<={L\quad {for}\quad {V_{DIG}(i)}}<=0}};} & (3)\end{matrix}$

[0013] where V_(DIG) is the output signal of the quantizer. The totalnumber of capacitances whose left capacitor plate in each case isconnected to the positive reference voltage source during theintegration phase and of capacitances whose left capacitor plate isconnected to the negative reference voltage source V_(REFN) during theintegration phase is constant here.

p(i)+n(i)=L=const.,  (4)

[0014] where L is the total number of capacitors.

[0015] So that the total charge is fully integrated, all capacitors areconnected to the input of the operational amplifier during theintegration phase.

[0016] The load of the reference voltage sources V_(REFP), V_(REFN) withthe prior art sigma-delta A/D converter shown in FIG. 2 is greatlysignal-dependent.

[0017] For V_(DIG)(i)˜V_(INA)(i) and V_(INA)(i)>0, the charge transferat the positive reference voltage source caused by the analog inputsignal V_(INA)(i) is calculated using the following equation:$\begin{matrix}{{| {{dq\_ V}_{REFP}(i)} | = {{{p(i)} \cdot ( {V_{REFP} - {V_{INA}(i)}} ) \cdot C_{jA}} = {{{round}\lbrack {{L/2} + {{L/2} \cdot \frac{V_{DIG}(i)}{V_{REF}}}} \rbrack} \cdot ( {V_{REFP} - {V_{INA}(i)}} ) \cdot { C_{jA} \sim( {{{L/2} \cdot V_{REF}} - {{L/2} \cdot {V_{INA}(i)}} + {{L/2} \cdot {V_{DIG}(i)}} - {{L/2} \cdot \frac{{V_{INA}(i)} \cdot {V_{DIG}(i)}}{V_{REF}}}} )} \cdot {{ C_{jA} \sim L}/2} \cdot C_{jA} \cdot V_{REF} \cdot ( {1 - \frac{{V_{INA}(i)}^{2}}{V_{REF}}} )}}};} & (5)\end{matrix}$

[0018] The charge transfer at the negative reference voltage source isobtained using the following equation: $\begin{matrix}{{| {{dq\_ V}_{REFN}(i)} | = {{{n(i)} \cdot ( | V_{REFN} \middle| {+ {V_{INA}(i)}}  ) \cdot C_{jA}} = {( {L - {{round}\lbrack {{L/2} + {{L/2} \cdot \frac{V_{DIG}(i)}{V_{REF}}}} \rbrack}} ) \cdot ( | V_{REFN} \middle| {+ {V_{INA}(i)}}  ) \cdot { C_{jA} \sim( {{{L/2} \cdot V_{REF}} + {{L/2} \cdot {V_{INA}(i)}} - {{L/2} \cdot {V_{DIG}(i)}} - {{L/2} \cdot \frac{{V_{INA}(i)} \cdot {V_{DIG}(i)}}{V_{REF}}}} )} \cdot {{ C_{jA} \sim L}/2} \cdot C_{jA} \cdot V_{REF} \cdot ( {1 - \frac{{V_{INA}(i)}^{2}}{{V_{REF}}^{2}}} )}}};} & (6)\end{matrix}$

[0019] If both analog signal inputs V_(INA)(i) and V_(INB)(i) areincluded, the value and the effective current load of the referencevoltage sources are doubled.

[0020] The effective current load of the reference voltage sources forthe prior art sigma-delta A/D converter, as illustrated in FIG. 2, isthen as follows: $\begin{matrix}{{{{Ceff}_{VREF}(i)} = {L \cdot C_{j} \cdot ( {1 - \frac{{V_{INA}(i)}^{2}}{{V_{REF}}^{2}}} )}};} & (7)\end{matrix}$

[0021] The maximum effective load of the reference voltage sources isobtained with V_(INA)(i)˜0 and is:

Ceff_max_(—) VREF=L·C _(j),  (8)

[0022] The minimum value of the effective load of the reference voltagesources is obtained for the value V_(INA)(i)˜V_(REF):

Ceff_min_(—) VREF=0.  (9)

[0023] As can be seen from the above equations, the current load of thereference voltage sources in the prior art sigma-delta A/D converter, asillustrated in FIG. 2, depends on the analog input signal. Thesignal-dependent load of the reference voltage sources leads tonon-linear distortions and limits the resolution of the prior artsigma-delta A/D converter.

[0024] It is therefore the object of the present invention to create asigma-delta A/D converter in which the current load of the referencevoltage sources is minimal.

[0025] According to the invention, this object is achieved by asigma-delta A/D converter having the features specified in claim 1.

[0026] Further advantageous refinements of the sigma-delta A/D converteraccording to the invention emerge from the subclaims.

[0027] The invention creates a sigma-delta A/D converter having at leastone analog signal input for applying an analog input signal, asubtraction element having a plurality of capacitors for sampling theinput signal during a sampling phase, it being possible during anintegration phase to switch the capacitors to reference voltage sourcesdepending on control signals, an integrator for integrating the outputsignal of the subtraction element during the integration phase, aquantizer for analog-to-digital conversion of the output signal of theintegrator for outputting a digitized output signal to a digital signaloutput, and having a control logic element for generating the controlsignals in such a way that the current load of the reference voltagesources is minimized during the integration phase.

[0028] In an advantageous refinement of the sigma-delta A/D converteraccording to the invention, first switching devices are switched bycontrol signals of the control logic element to connect the referencevoltage sources to the capacitors during the integration phase.

[0029] In a further advantageous refinement of the sigma-delta A/Dconverter according to the invention, second switching devices areswitched by control signals of the control logic element to connect thecapacitors to the analog signal input during a sampling phase.

[0030] In a further advantageous refinement of the sigma-delta A/Dconverter according to the invention, third switching devices areswitched by control signals of the control logic element to connect thecapacitors to the integrator during the integration phase.

[0031] The control signals are preferably generated depending on thedigitized output signal of the quantizer, the potential differencebetween the reference voltage sources and the number of capacitors.

[0032] In a preferred embodiment of the sigma-delta A/D converteraccording to the invention, the capacitors have the same capacitance.

[0033] Three reference voltage sources are preferably provided.

[0034] In a preferred embodiment of the sigma-delta A/D converteraccording to the invention, a first reference voltage source having areference potential, a second reference voltage source having a positivepotential and a third reference voltage source having a negativepotential are provided.

[0035] The negative potential of the third reference voltage source andthe positive potential of the second reference voltage source arepreferably symmetrical to the reference potential of the first referencevoltage source.

[0036] The sigma-delta A/D converter according to the invention ispreferably of a differential design with two analog signal inputs.

[0037] A low-pass filter is preferably connected downstream of thedigital signal output.

[0038] In a preferred embodiment of the sigma-delta A/D converteraccording to the invention, the integrator has an operational amplifierand at least one integration capacitor.

[0039] The quantizer preferably has a relatively low signal resolutionin comparison with the signal resolution of the sigma-delta A/Dconverter according to the invention.

[0040] The operational amplifier within the integrator preferably has avery high-resistance signal input.

[0041] A preferred embodiment of the sigma-delta A/D converter accordingto the invention is described below to illustrate the key features ofthe invention with reference to the attached drawings, in which:

[0042]FIG. 1 shows a block circuit diagram of a conventional sigma-deltaA/D converter;

[0043]FIG. 2 shows a circuit diagram of a sigma-delta A/D converteremploying SC circuitry according to the prior art;

[0044]FIG. 3 shows a block circuit diagram of a sigma-delta A/Dconverter according to the invention;

[0045]FIG. 4 shows a circuit diagram of a preferred embodiment of thesigma-delta A/D converter according to the invention;

[0046]FIG. 5 shows a time sequence diagram for comparing the currentload of the reference voltage sources in the sigma-delta A/D converteraccording to the invention against that of a conventional sigma-deltaA/D converter;

[0047]FIG. 6 shows a block circuit diagram of the sigma-delta A/Dconverter according to the invention.

[0048] The sigma-delta A/D converter according to the invention containsat least two analog signal inputs 1, 2 for applying analog input signalsto a subtraction element or subtraction circuit 3 which contains aplurality of capacitors for sampling the analog input signals during asampling phase. During an integration phase the capacitors contained inthe subtraction element 3 are switched via lines 4, 5, 6 to referencevoltage sources 7, 8, 9 depending on control signals. The sigma-deltaA/D converter according to the invention also contains an integrator 10which is connected on the input side to the subtraction element 3 vialines 11. The integrator temporally integrates the output signal outputfrom the subtraction element 3 during the integration phase and outputsthe integrated signal to a quantizer 13 via lines 12. The quantizer 13performs analog-to-digital conversion of the output signal of theintegrator 10 to output a digitized output signal to a digital signaloutput 14. The output 14 of the sigma-delta A/D converter according tothe invention is fed back to the input of a control logic element 16 viaa feedback line 15. The control logic element controls switching deviceswithin the subtraction element 3 via control lines 17.

[0049] In the preferred embodiment of the sigma-delta A/D converteraccording to the invention shown in FIG. 3, three reference voltagesources 7, 8, 9 are provided. The reference voltage source 7 is herepreferably a positive reference voltage source having a positivepotential, the second reference voltage source 8 has a referencepotential and the third reference voltage source 9 is preferably anegative reference voltage source having a negative potential. Thepositive potential of the positive reference voltage source 7 and thenegative potential of the negative reference voltage source 9 arepreferably symmetrical to the reference potential of the referencevoltage source 8. The reference potential is ground potential forexample.

[0050]FIG. 4 shows a circuit diagram of a preferred embodiment of thesigma-delta A/D converter according to the invention illustrated as ablock circuit diagram in FIG. 3.

[0051] The subtraction element 3 contains a plurality of capacitors 20for charge storage during a sampling phase. The first group ofcapacitors 20-1 A, 20-2 A . . . 20-L A can be switched by switchingdevices 21-1 A, 21-2 A . . . 21-L A to the first analog signal input 1,at which the analog signal V_(INA) is present. The second group ofcapacitors 20-1 B, 20-2 B . . . 20-L B can be switched by switchingdevices 21-1 B, 21-2 B . . . 21-L B to the second analog signal input 2,at which the second analog input signal V_(INB) is present.

[0052] The capacitors of the subtraction element 3 can also be connectedon the input side by controllable switching devices 22-1 A, 22-2 A . . .22-L A and 22-1 B, 22-2 B . . . 22-L B to the positive reference voltagesource 7 via the line 4 depending on control signals of the controllogic element 16.

[0053] The capacitors can be switched by switching devices 23-1 A, 23-2A . . . 23-L A and 23-1 B, 23-2 B 23-L B to the second reference voltagesource 8 via the line 5.

[0054] The capacitors can also be switched by switching devices 24-1 A,24-2 A 24-L A and 24-1 B, 24-2 B . . . 24-L B to the negative referencevoltage source 9 via the line 6.

[0055] On the output side the capacitors of the subtraction element 3can be switched by switching devices 25-1 A, 25-2 A . . . 25-L A and25-1 B, 25-2 B 25-L B to a common ground line 26.

[0056] The first group 20-1 A, 20-2 A 20-L A of capacitors 20 of thesubtraction element 3 can be connected by switching devices 27-1 A, 27-2A . . . 27-L A via a line 11A to the non-inverting input 28 of theoperational amplifier 29 within the integrator 10. The second group 20-1B, 20-2 B . . . 20-L B can be connected by switching devices 27-1 B,27-2 B . . . 27-L B via a line 11B to the inverting input 30 of theoperational amplifier 29 within the integrator 10. The connecting line11A between the subtraction element 3 and the integrator 10 is connectedvia a line 31 to a first integration capacitor 32 of the integrator 10,with the integration capacitor 32 being connected on the output side viaa line 33 to the first output line 12A of the integrator 10.

[0057] The connecting line 11B between the subtraction element 3 and theintegrator 10 is connected via a line 34 to a second integrationcapacitor 35 of the integrator 10, which is connected on the output sidevia a line 36 to the second output line 12B of the integrator 10. On theoutput side the operational amplifier 29 of the integrator 10 isconnected to the quantizer 13 via the output lines 12A, 12B.

[0058] During the sampling phase all capacitors of the first group 20-1A, 20-2 A . . . 20-L A are connected to the first analog signal input 1by closing the switching devices 21-1 A, 21-2 A . . . 21-L A, and thesecond group of capacitors 20-1 B, 20-2 B . . . 20-L B are connected tothe second analog signal input 2 by closing the switching devices 21-1B, 21-2 B . . . 21-L B. The first group of capacitors 20-1 A, 20-2 A . .. 20-L A is charged during the sampling phase in accordance with thefirst analog input signal V_(INA) and the second group of capacitors20-1 B, 20-2 B . . . 20-L B is charged during the sampling phase inaccordance with the second analog input signal V_(INB). During thesampling phase, the switching devices 25-1 A, 25-2 A . . . 25-L A and25-1 B, 25-2 B . . . 25-L B are closed so that the capacitors areconnected on the output side to the ground line 26. Upon completion ofthe sampling phase, the capacitors are disconnected from the analogsignal inputs by opening the switching devices 21-1 A, 21-2 A . . . 21-LA and 21-1 B, 21-2 B . . . 21-L B. At the same time the ground switchingdevices 25-1 A, 25-2 A . . . 25-L A and 25-1 B, 25-2 B . . . 25-L B areopened to disconnect the capacitors from the ground line 26. Theswitching devices are controlled by the control logic element viacontrol lines 17.

[0059] In the ensuing integration phase, depending on the value of thedigitized feedback signal applied to the lines 15, the left capacitorplates of the capacitors 20 are connected to the reference voltagesources 7, 8, 9 under the control of the control logic element 16.Depending on the digitized feedback signal applied, the control logicelement 16 controls the switching devices 22 to connect to the positivereference voltage source 7, the switching devices 23 to connect thecapacitors to the reference voltage source 8, and the switching devices24 to connect the capacitors to the negative reference voltage source 9.

[0060] Upon completion of the integration phase, a voltage V_(OUTP)(i)is present at the output of the integrator 10 between the lines 12A,12B, which voltage depends on the preceding value V_(OUTP)(i−1), theinput voltage V_(INA) (i−½), the number n of capacitors whose leftcapacitor plate is connected to the negative reference voltage sourceduring the integration phase, the number p of capacitors whose leftplate is connected to the positive reference voltage source during theintegration phase, and the number m of capacitors whose left capacitorplate is connected to the middle reference potential of the referencevoltage source 8 during the integration phase.

[0061] The output voltage of the integrator 10 after completion of theintegration phase V_(OUTP)(i) is obtained using the following equation:$\begin{matrix}{{{V_{OUTP}(i)} = { {{V_{OUTP}( {i - 1} )} + {{V_{INA}( {i - {1/2}} )} \cdot \frac{L \cdot C_{jA}}{C_{int}}} - {{p(i)} \cdot}} \middle| \quad V_{REFP} \middle| {{\cdot \frac{C_{jA}}{C_{int}}} + {{n(i)} \cdot}} \middle| V_{REFN} \middle| {{\cdot \frac{C_{jA}}{C_{int}}} - {m \cdot V_{GND} \cdot \frac{C_{jA}}{C_{int}}}}  = {{{V_{OUTP}( {i - 1} )} + {{V_{INA}( {i - {1/2}} )} \cdot \frac{L \cdot C_{jA}}{C_{int}}} - {{( {{p(i)} - {n(i)}} ) \cdot V_{REF} \cdot \frac{C_{jA}}{C_{int}}}\quad {with}\quad V_{REF}}} = {V_{REFP} = | V_{REFN} |}}}};} & (10)\end{matrix}$

[0062] The number p of capacitors 20 whose left capacitor plate isconnected to the positive reference voltage source 7 during theintegration phase by closing the switches 22 is obtained using thefollowing rule: $\begin{matrix}{{{p(i)} = {{{round}\lbrack {L \cdot \frac{V_{DIG}(i)}{V_{REF}}} \rbrack}<=L}},{{m(i)} = {L - {p(i)}}},{{{n(i)} = {{0\quad {for}\quad {V_{DIG}(i)}}>=0}};}} & (11)\end{matrix}$

[0063] where V_(DIG)(i) is the digitized output signal of the quantizer13. The value is rounded to the nearest integer.

[0064] The number n of capacitors 20 whose left capacitor plate isconnected to the negative reference voltage source during theintegration phase is obtained using the following rule: $\begin{matrix}{{{n(i)} = {{{{round}\lbrack {L \cdot \frac{V_{DIG}(i)}{V_{REF}}} \rbrack}<={L\quad {m(i)}}} = {L - {n(i)}}}},{{{p(i)} = {{0\quad {for}\quad {V_{DIG}(i)}}<=0}};}} & (12)\end{matrix}$

[0065] where V_(DIG) is the digitized output signal of the quantizer 13.

[0066] A total of (2L+1) different feedback values is obtained.

[0067] So that the charge can be fully integrated, during theintegration phase all capacitors are connected to the operationalamplifier 29 by the switching devices 27. AssumingV_(DIG)(i)˜V_(INA)(i), V_(INA)(i)>0, the current load of the referencevoltage sources is: $\begin{matrix}{{| {{dq\_ V}_{REFP}(i)} | = {{p(i)} \cdot ( {V_{REFP} - {V_{INA}(i)}} ) \cdot { C_{jA} \sim L} \cdot C_{j} \cdot \frac{V_{DIG}(i)}{V_{REF}} \cdot ( {V_{REFP} - {V_{INA}(i)}} )}};} & (13) \\{{| {{dq\_ V}_{OND}(i)} | =  {{m(i)} \cdot} \middle| ( {V_{OND} - {V_{INA}(i)}} ) \middle| {{{{\cdot { C_{jA} \sim L}} \cdot C_{jA}} \cdot ( {1 - \frac{V_{DIG}(i)}{V_{REF}}} )} \cdot {V_{INA}(i)}} };} & (14) \\{{| {{dq\_ V}_{REFN}(i)} | = 0};} & (15)\end{matrix}$

[0068] The differential load of the reference voltage sources is:$\begin{matrix}\begin{matrix}{{{{dq\_ V}_{REFP}{\_ diff}(i)}} = \quad {{{{dq\_ V}_{REFN}{\_ diff}(i)}} = {{{{dq\_ V}_{REFP}(i)}} +}}} \\{\quad {{{{dq\_ V}_{REFN}(i)}} =}} \\{{= \quad {L \cdot C_{i} \cdot \frac{{V_{DIG}(i)}}{V_{REF}} \cdot ( {V_{REF} - {{V_{INA}(i)}}} )}};}\end{matrix} & (16)\end{matrix}$

[0069] The charge transfer at the reference potential reference voltagesource 8 caused by the first analog input signal V_(INA)(i) and thesecond analog input signal V_(INB)(i) cancel each other out:

|dq _(—) V _(GND) diff(i)|=0;  (17)

[0070] Accordingly, the effective load of the reference voltage sourcesin the sigma-delta A/D converter according to the invention is obtained:$\begin{matrix}{{{{Ceff}_{VREF}(i)} = {L \cdot C_{jA} \cdot \frac{V_{DIG}(i)}{V_{REF}} \cdot ( {V_{REF} - {{V_{INA}(i)}}} )}};} & (18)\end{matrix}$

[0071] The maximum effective load of the reference voltage sources isobtained with:

|V _(DIG)(i)|˜|V_(INA)(i)|˜V _(REF)/2  (19)

[0072] The maximum effective load of the reference voltage sources ishere:

Ceff_max_(—) VREF=L/4·C _(j):  (20)

[0073] The minimum effective load of the reference voltage sources isobtained for:

|V _(DIG)(i)|˜|V _(INA)(i)|˜0or V _(REF)  (21)

[0074] where the minimum effective load of the reference voltage sourcesis:

Ceff_min_(—) VREF=0.  (22)

[0075] As can be seen from the above equations, the maximum current loadof the reference voltage sources is reduced by a factor of 4 incomparison with the prior art sigma-delta A/D converter as illustratedin FIG. 2. By reducing the maximum current load of the reference voltagesources, the signal-dependent non-linearities are significantly reduced.Conversely, the reference voltage sources can be dimensioned to besmaller by a factor of 4 for the same level of non-linearities. Byreducing the load of the reference voltage sources, the non-lineardistortions of the sigma-delta A/D converter according to the inventionare significantly reduced in comparison with conventional sigma-deltaA/D converters, and the resolution of the sigma-delta A/D converteraccording to the invention is increased.

[0076] In the sigma-delta A/D converter according to the invention, theload of the reference voltage sources is approximately 0, that is to saysignal-independent, when input signals with a small signal amplitudeV_(INA)(i)˜0 are applied.

[0077] A further advantage of the sigma-delta A/D converter according tothe invention is that the number of possible feedback values isincreased from (L+1) to (2L+1) different feedback values for the samenumber of capacitors 20 within the subtraction element 3.

[0078] Moreover, the sigma-delta A/D converter according to theinvention, as illustrated in FIG. 4, has further additional advantageousfeatures. By using the additional reference voltage source 8 withreference potential, with a differential implementation of thesigma-delta A/D converter according to the invention no non-linearitiesare produced in the case where the positive potential of the positivereference voltage source 7 is not symmetrical to the negative potentialof the negative reference voltage source 9, that is to say when(V_(EFP)−V_(GND)) is not equal to (V_(GND)−V_(REFN)), as is demonstratedin the following equations: $\begin{matrix}\begin{matrix}{{{d\_ V}_{OUTP}(i)} = \quad {{( {{V_{INA}( {i - {1/2}} )} - V_{GND}} ) \cdot \frac{L \cdot C_{jA}}{C_{ME}}} - {{p(i)} \cdot}}} \\{\quad {{( {V_{REFP} - V_{GND}} ) \cdot \frac{C_{jA}}{C_{int}}} - {{m(i)} \cdot ( {V_{GND} - V_{GND}} ) \cdot \frac{C_{jA}}{C_{in}}}}} \\{{{d\_ V}_{OUTN}(i)} = \quad {{( {{V_{INB}( {i - {1/2}} )} - V_{GND}} ) \cdot \frac{L \cdot C_{jA}}{C_{mi}}} - {{p(i)} \cdot}}} \\{\quad {{( {V_{REFN} - V_{GND}} ) \cdot \frac{C_{jA}}{C_{mi}}} - {{m(i)} \cdot ( {V_{GND} - V_{GND}} ) \cdot \frac{C_{jA}}{C_{in}}}}} \\{{{d\_ V}_{OUT}(i)} = \quad {{{{d\_ V}_{OUTP}(i)} - {{d\_ V}_{OUTN}(i)}} = ( {{V_{INA}( {i - {1/2}} )} -} }} \\{{{\quad  {V_{INB}( {i - {1/2}} )} )} \cdot \frac{L \cdot C_{jA}}{C_{mi}}} - {{p(i)} \cdot ( {{V_{REFP} - {V_{REF} \cdot \frac{C_{jA}}{C_{mi}}}};} }}\end{matrix} & (25)\end{matrix}$

[0079] In the preferred embodiment of the sigma-delta A/D converteraccording to the invention shown in FIG. 4, three reference voltagesources are provided.

[0080] With alternative embodiments, further reference voltage sourceswith further reference potentials may be used.

[0081] Another key feature of the sigma-delta A/D converter according tothe invention is that the analog input signal (V_(INA), V_(INB)) need nolonger fully charge the capacitors 20 during the sampling phase. Ratherthe charge is balanced when the left capacitor plate of a capacitor isconnected by the switching devices 21 to the analog input signal and theright capacitor plate of the capacitors 20 is connected by the switchingdevices 25 to the ground line 26.

[0082] The charging at the beginning of the sampling phase is:

q _(IN)(i+)=V _(DIG)(i)xLxC _(j);  (26)

[0083] So that all capacitors are charged up to the charge

q _(IN)(i+½)=V _(IN)(i+½)·L·C _(j)  (27)

[0084] the analog input signal V_(IN)(i) must supply the remainingcharge:

d _(—) q _(IN)(i+½)=q _(IN)(i+½)−q _(IN)(i+)=[V _(IN)(i+½)−V_(DIG)(i)]·L·C _(j)  (28)

[0085] In the case of a high oversampling of the analog input signal bythe sigma-delta A/D converter according to the invention and a highresolution with a large number of capacitors, the followingapproximation applies:

V _(DIG)(i)→V_(IN)(i+½)  (29)

[0086] where the charge transfer approaches 0:

d _(—) q _(IN)(i)→0.  (30)

[0087] In this case the current load of the signal source is negligibleand signal-independent.

[0088]FIG. 5 shows a time sequence diagram for illustrating the chargeload of the reference voltage sources of the sigma-delta A/D converteraccording to the invention in comparison with a conventional sigma-deltaA/D converter depending on the absolute value of an analog input signal.

[0089] The signal a represents the absolute value of an analog inputsignal. The example in FIG. 5 shows a sinusoidal analog input signalV_(IN).

[0090] The curve b shows the charge load of a conventional prior artsigma-delta A/D converter as illustrated in FIG. 2.

[0091] The curve c shows the charge load of the reference voltagesources of the sigma-delta A/D converter according to the invention asshown in FIG. 4.

[0092] As can be seen by comparing the curves b and c, the charge loador the current load of the reference voltage sources in the sigma-deltaA/D converter according to the invention is significantly reduced incomparison with conventional sigma-delta A/D converters. In thesigma-delta A/D converter according to the invention, the maximumcurrent load of the reference voltage sources can be reduced by up to afactor of 4.

1. Sigma-delta A/D converter having at least one analog signal input (1,2) for applying an analog input signal, at least one subtraction element(3) having a plurality of capacitors (20) for sampling the input signalduring a sampling phase, it being possible during an integration phaseto switch the capacitors (20) to reference voltage sources (7, 8, 9)depending on control signals, at least one integrator (10) forintegrating the output signal of the subtraction element (3) during theintegration phase, a quantizer (13) for analog-to-digital conversion ofthe output signal of the integrator (10) for outputting a digitizedoutput signal to a digital signal output (14), and having a controllogic element (16) for generating the control signals in such a way thatthe current load of the reference voltage sources (7, 8, 9) is minimizedduring the integration phase.
 2. Sigma-delta A/D converter according toclaim 1, characterized in that the control signals switch firstswitching devices (21) for connecting the capacitors (20) to the analogsignal input (1, 2) during a sampling phase.
 3. Sigma-delta A/Dconverter according to claim 1 or 2, characterized in that the controlsignals switch second switching devices (22, 23, 24) for connecting thereference voltage sources (7, 8, 9) to the capacitors (20) during theintegration phase.
 4. Sigma-delta A/D converter according to one of thepreceding claims, characterized in that the control signals switch thirdswitching devices (27) for connecting the capacitors (20) to theintegrator (10) during the integration phase.
 5. Sigma-delta A/Dconverter according to one of the preceding claims, characterized inthat the control signals are generated depending on the digitized outputsignal of the quantizer (13), the potential difference between thereference voltage sources (7, 8, 9) and the number of capacitors (20).6. Sigma-delta A/D converter according to one of the preceding claims,characterized in that the capacitors (20) have the same capacitance ineach case.
 7. Sigma-delta A/D converter according to one of thepreceding claims, characterized in that three reference voltage sources(7, 8, 9) are provided.
 8. Sigma-delta A/D converter according to one ofthe preceding claims, characterized in that the first reference voltagesource (7) has a positive potential, the second reference voltage source(8) has a reference potential and the third reference voltage source (9)has a negative potential.
 9. Sigma-delta A/D converter according toclaim 8, characterized in that the positive potential of the firstreference voltage source (7) and the negative potential of the thirdreference voltage source (9) are symmetrical to the reference potentialof the second reference voltage source (8).
 10. Sigma-delta A/Dconverter according to one of the preceding claims, characterized inthat the sigma-delta A/D converter is of a differential design with twoanalog signal inputs (1, 2).
 11. Sigma-delta A/D converter according toone of the preceding claims, characterized in that a low-pass filter isconnected downstream of the digital signal output (14).
 12. Sigma-deltaA/D converter according to one of the preceding claims, characterized inthat the integrator (10) has an operational amplifier (29) and at leastone integration capacitor (32, 35).
 13. Sigma-delta A/D converteraccording to one of the preceding claims, characterized in that thequantizer (13) has a low signal resolution.
 14. Sigma-delta A/Dconverter according to one of the preceding claims, characterized inthat the operational amplifier (29) has a high-resistance signal input.